This page covers the AI compute layer: merchant accelerators, custom AI ASICs, and rack-scale systems that turn model code into tensor math inside data centers. An accelerator is a packaged processor built around a compute die, nearby high-bandwidth memory, dense package wiring, board-level power delivery, high-speed links, firmware, compilers, and cluster software. A custom ASIC is a purpose-built chip shaped around one operator's training, inference, networking, or data-movement path. These components sit inside AI servers and racks, where they load model weights, execute matrix multiplication and attention kernels, move activations and gradients across chips, serve tokens and embeddings, and connect to storage, networking, cooling, and facility power. The node gets paid when hyperscaler, AI-cloud, model-builder, and enterprise capex becomes shipped chips, accelerator modules, rack systems, AI semiconductor revenue, durable gross margin, free cash flow, and per-share value. NVDA has the clearest reported Data Center revenue, gross margin, and free cash flow evidence; AVGO has the strongest custom-silicon route but heavier customer concentration; AMD is the challenger route that still needs more proof on accelerator revenue, software adoption, and warrant-adjusted economics; MRVL is the smaller custom-silicon and data-center connectivity route, with strong data-center mix but a higher valuation and cash-conversion proof burden.
What the stack is: merchant GPUs and accelerators are flexible AI processors sold across many customers; custom silicon is an ASIC built for a specific buyer, workload, memory hierarchy, interconnect, and software environment; rack-scale systems combine compute trays, CPUs, NICs, switches, cables, power shelves, cooling, and management software into deployable AI capacity.
What it does: the stack performs tensor math for training and inference, including transformer layers, attention, matrix multiplication, embeddings, recommendation ranking, image generation steps, gradient synchronization, and key-value cache access.
Main physical pieces: compute die, HBM stacks, package substrate, interposer or other dense package wiring, accelerator module, server board, voltage regulators, NICs, scale-up links, Ethernet or InfiniBand adapters, cooling interface, firmware, kernel libraries, compilers, and cluster schedulers.
Where it sits: the compute die and HBM sit inside the accelerator package; the package mounts on an accelerator board or server tray; multiple trays connect inside a rack; racks connect through cluster networking to storage systems, CPU hosts, data pipelines, and facility power and cooling.
How AI infrastructure uses it: training jobs stream tokenized data from storage into CPU memory and accelerator HBM, run repeated forward and backward passes, synchronize partial results across thousands of chips, and write checkpoints back to storage; inference jobs keep model weights and key-value caches close to compute so servers can return tokens, embeddings, rankings, or generated media with low latency.
Terms used later: HBM means stacked DRAM inside the accelerator package for high bandwidth; ASIC means a purpose-built chip; rack-scale means the sellable system is the full rack or tray cluster, not only the chip; custom silicon revenue is semiconductor revenue tied to customer-specific AI or networking programs.
Report boundary: this node is a tactical report layer. It ranks the current value-chain basket, setup labels, confirmation triggers, invalidation levels, and chart provenance. Durable research, claim IDs, raw source registries, and sector thesis maintenance stay in the linked knowledge pages. Price and volume context comes from read-only discovery daily_ohlc with completed weekly setup rows through 2026-06-05 and stored daily rows through 2026-06-08.
Current Setup
AI compute profit poolOrders need to become shipped systems at durable margin.
Accelerator suppliers are closest to the direct AI infrastructure spend, but the read depends on shipment conversion, customer breadth, export access, and free cash flow after supply commitments.
Reported proofNVDA and AVGO carry the cleanest evidence.
Data Center revenue, AI semiconductor revenue, gross margin, and FCF are visible.
Conversion gateAMD and MRVL still need broader confirmation.
Watch accelerator revenue detail, software adoption, customer warrants, and cash conversion.
Primary constraintHyperscaler leverage can dilute supplier capture.
Internal silicon, export controls, HBM and packaging, power, and rack complexity remain live risks.
Buyer budgetHyperscalers + AI cloud
Stack deliveredGPU, ASIC, HBM, rack
Accounting proofRevenue, GM, FCF
Live watchChina, supply, breadth
Accelerator and custom-silicon suppliers sit closest to the direct AI infrastructure profit pool. Their chips decide how much training and inference capacity customers can deploy, and their economics are visible in Data Center revenue, AI semiconductor revenue, gross margin, operating cash flow, and customer breadth. The node is most investable when orders become shipped systems at durable margin instead of only larger supply commitments, inventory, or customer-specific engineering spend.
The strongest evidence is reported rather than only planned. NVIDIA's May 20, 2026 release showed Q1 FY2027 revenue of $81.6B, Data Center revenue of $75.2B, and 75.0% non-GAAP gross margin. Broadcom's June 3, 2026 release showed Q2 FY2026 AI semiconductor revenue of $10.8B, Q2 free cash flow of $10.262B, and Q3 AI semiconductor revenue expected at $16.0B. AMD's local lane shows Q1 2026 Data Center revenue of $5.775B, Q2 revenue guidance near $11.2B, and Meta/OpenAI-linked MI450/Helios visibility. Marvell's local lane and official Q1 FY2027 release show Data Center revenue of $1.833B, 76% of total revenue, and FY2027/FY2028 revenue outlooks tied to optics, switching, storage, custom silicon, and NVIDIA ecosystem adoption. The next positive proof is shipment conversion, margin durability, broader customer evidence, and FCF after working-capital and supply commitments.
The same buyers that fund AI capex also have leverage. Export controls can remove China demand or strand inventory; large hyperscalers can dual-source, negotiate price, or push more workloads to internal silicon; HBM, TSMC, CoWoS, substrate, networking, and data-center power bottlenecks can delay shipments; rack-scale systems can dilute margin if complexity rises; AMD warrants and commitments can dilute per-share capture if revenue does not scale. MRVL adds customer-warrant, China-destination shipment, capacity-deposit, Celestial integration, preferred-conversion, valuation, and high-beta chart risk. Watch customer concentration, China assumptions, purchase obligations, AI semiconductor guide quality, and whether AMD and MRVL digest extended charts without losing Data Center evidence.
Technical setup references use completed weekly bars aggregated from discovery daily_ohlc through 2026-06-05. The local store also has partial current-week daily rows through 2026-06-08; those rows are recorded in Source Trail but not used for weekly volume labels. Fundamental claims route to the AI Capex theme, Information Technology sector lane, linked security lanes, and the official releases cited in Source Trail.
Basket
This basket is inherited from the AI Capex parent report and hand-curated against local knowledge coverage. Ranking uses node economics and source-backed conversion first, then technical timing. NVDA ranks first because reported Data Center scale, margin, and cash flow are strongest. AVGO ranks second because the custom ASIC evidence is strong but concentrated. AMD ranks third because the challenger setup has real Data Center momentum but more proof burden around Instinct revenue, software, warrants, commitments, and customer breadth. MRVL ranks fourth as a local discovery-covered custom XPU and AI data-center silicon route, while QCOM remains watch-only until rack-scale AI accelerator shipments and revenue economics are disclosed.
Full-stack merchant accelerator platform with the clearest reported Data Center scale.
Market cap$5.23T
Next earningsAug 26, 2026
Latest qtr revenue$81.6B
Role in stack
NVIDIA sells accelerated-computing platforms to hyperscalers, AI model builders, enterprises, OEMs, ODMs, and public-sector customers. The route to economics is GPUs, networking, rack-scale systems, CUDA/software, and the Rubin roadmap becoming Data Center revenue, gross margin, free cash flow, and customer breadth.
Revenue mix
The June 7 local lane frames NVIDIA as primarily a Data Center AI infrastructure company. The official May 20, 2026 release reported Q1 FY2027 Data Center revenue of $75.2B and total revenue of $81.6B.
Proof burden
Export access, largest-customer concentration, memory/packaging supply, and purchase obligations control conversion. The Q2 FY2027 guide assumes no China Data Center compute revenue, so export access remains a live gate.
Custom AI accelerator and networking route with strong revenue evidence but concentrated buyers.
Market cap$2.04T
Next earningsSep 2026 est.
Latest qtr revenue$22.187B
Role in stack
Broadcom sells custom AI accelerator silicon and AI networking into large hyperscaler programs. Value converts when customer-specific ASIC and Ethernet designs become AI semiconductor revenue, adjusted EBITDA, free cash flow, and durable program breadth.
Revenue mix
Q2 FY2026 revenue was split between Semiconductor Solutions at $15.009B and Infrastructure Software at $7.178B. AI semiconductor revenue was $10.8B, while VMware-led software is the cash-flow stabilizer rather than the node exposure itself.
Proof burden
Q3 revenue guidance is about $29.4B and Q3 AI semiconductor revenue is expected at $16.0B. Top-customer exposure, TSMC and advanced-packaging access, VMware retention, leverage, SBC, and buyback discipline control conversion.
Challenger accelerator route with Data Center momentum and a higher proof burden.
Market cap$742B
Next earningsLate Jul 2026 est.
Latest qtr revenue$10.253B
Role in stack
AMD sells EPYC server CPUs, Instinct accelerators, and rack-scale AI systems to hyperscalers, AI customers, and enterprise/server buyers. Economics convert when Data Center growth becomes visible accelerator revenue, gross margin, free cash flow, and per-share value.
Revenue mix
Q1 2026 Data Center revenue was $5.775B, or 56.3% of company revenue, with Client/Gaming and Embedded providing diversification. The lane does not fully separate EPYC CPU, Instinct accelerator, and rack-scale system revenue.
Proof burden
Q2 guidance was about $11.2B of revenue with 56% non-GAAP gross margin. Meta/OpenAI-linked visibility and MI450/Helios timing support the setup, but warrants, commitments, revenue granularity, ROCm/software maturity, HBM/component costs, Nvidia competition, and export controls keep the proof burden high.
Custom XPU, switching, storage, and connectivity route into AI clusters.
Market cap$149B
Next earningsLate Aug 2026 est.
Latest qtr revenue$2.418B
Role in stack
Marvell sells AI data-center connectivity, switching, storage, and custom silicon into hyperscaler AI cluster programs. Theme pressure becomes company economics when AI bookings and design wins convert into Data Center revenue, gross margin, operating cash flow, and durable FY2027-FY2028 guidance.
Revenue mix
Q1 FY2027 revenue was $2.418B; Data Center was $1.833B, or 76% of revenue; communications and other was $585.1M. FY2026 Data Center revenue was 74% of revenue.
Proof burden
Q2 FY2027 guide is $2.7B +/- 5%, FY2027 revenue outlook is nearly $11.5B, and FY2028 guidance is $16.5B. Conversion gates are customer concentration, warrants, China-destination shipment exposure, export controls, Celestial AI integration, capacity deposits, NVIDIA ecosystem adoption, and high valuation expectations.
MRVL is included for custom XPU/custom AI silicon and data-center connectivity exposure, not as a pure GPU peer. Header market caps use local discovery instruments.market_cap values queried on 2026-06-13; next-earnings fields are confirmed where available and otherwise marked as estimates. Watch-only: QCOM. Rejected or companion routes: ARM and TSM lack local discovery instrument or OHLC coverage; INTC remains roadmap-heavy; AMAT, CAMT, and MPWR belong in semicap and packaging; CSCO, ANET, ALAB, and CRDO belong in networking and interconnect.
What Confirms Or Weakens
AreaWhat confirmsWhat weakens or invalidatesWatch next
01Node thesis
Demand stays funded
What confirms
NVIDIA Data Center revenue, Broadcom AI semiconductor revenue, AMD Data Center/Instinct evidence, and Marvell Data Center revenue grow while hyperscaler and AI-cloud capex plans remain funded.
What weakens or invalidates
Hyperscaler capex digestion, internal ASIC substitution, utilization warnings, or delayed AI clusters reduce order visibility for merchant and custom silicon suppliers.
Watch next
NVIDIA Blackwell/Rubin
Broadcom Q3 AI guide
AMD MI450/Helios
MRVL FY2027/FY2028 guide conversion
02AI revenue and margin mechanism
Revenue becomes cash
What confirms
Revenue converts into gross margin and FCF: NVIDIA holds around mid-70s margin, Broadcom validates AI revenue and adjusted EBITDA, AMD moves toward its Q2 revenue and 56% non-GAAP gross-margin guide, and MRVL turns Data Center mix into margin and operating cash flow.
What weakens or invalidates
Margin misses, inventory or receivable drag, weak FCF conversion, high SBC, warrant dilution, capacity deposits, Celestial accounting, or buybacks that fail to offset dilution weaken per-share economics.
Watch next
Segment revenue
Gross margin
Operating cash flow
Purchase commitments
Share count
03Customer concentration and substitution
Buyer power check
What confirms
Large buyers keep ordering merchant accelerators and custom ASIC programs while customer breadth improves or disclosure becomes clearer.
What weakens or invalidates
A small number of buyers gain pricing power, push more work to internal TPUs, Trainium, Maia, MTIA, or other custom ASICs, delay deployments, or negotiate economics that shift value away from public suppliers.
Watch next
NVDA direct-customer concentration
AVGO top-customer disclosure
AMD warrant milestones
MRVL customer warrants
Hyperscaler internal silicon
04Supply and policy gate
Shipments stay available
What confirms
HBM, packaging, foundry capacity, networking attach, power delivery, and export licenses support shipments without new inventory charges or lost revenue assumptions.
What weakens or invalidates
China/export restrictions, TSMC or CoWoS limits, HBM allocation, substrate shortages, data-center power delays, or MRVL China-destination exposure stop orders from becoming revenue at planned margin.
Watch next
BIS/export updates
TSMC and packaging commentary
HBM allocation
Capacity deposits
China revenue assumptions
05Stale condition
Refresh trigger
What confirms
Discovery daily_ohlc remains current through 2026-06-08 and completed weekly setup rows use the 2026-06-05 close; linked knowledge and bounded official checks cover the latest material company events reviewed here.
What weakens or invalidates
A new completed weekly close, earnings release, 10-Q, export-policy update, customer program disclosure, or supply-chain update arrives before this page is refreshed.
Watch next
Discovery refresh
NVDA/AVGO/AMD/MRVL/QCOM source routes
Official-release checks
Setup levels
Source Trail
Canonical Thesis
AI Capex Cycle for the cross-sector capex chain, proof burden, and supplier routing.
NVDA security lane for the durable Data Center, margin, customer concentration, export, and supply-obligation evidence spine.
AVGO security lane for custom AI silicon, AI networking, VMware cash flow, customer concentration, TSMC dependence, leverage, and SBC evidence.
AMD security lane for Data Center, EPYC, Instinct, MI450/Helios, customer warrants, commitments, export controls, and software proof burden.
MRVL security lane for Data Center mix, custom silicon, optics and switching, NVIDIA ecosystem evidence, Celestial AI, capacity deposits, China-destination shipments, and valuation proof burden.
QCOM security lane for watch-only custom silicon optionality, handset/licensing exposure, and the missing customer, product, revenue, margin, and contract-duration details.
MSFT, GOOGL, META, AMZN, and CRWV are demand and procurement routes, not basket members.
Bounded Official Check
NVIDIA May 20, 2026 Q1 FY2027 earnings release: used with the June 7 local NVDA lane for Q1 FY2027 revenue of $81.6B, Data Center revenue of $75.2B, GAAP/non-GAAP gross margin of 74.9%/75.0%, Q1 operating cash flow of $50.3B, and Q2 FY2027 revenue guidance of $91.0B +/- 2% with no China Data Center compute revenue assumed.
Broadcom June 3, 2026 Q2 FY2026 earnings release: bounded official refresh because the local AVGO lane predates Q2 results. The release reported Q2 revenue of $22.187B, AI semiconductor revenue of $10.8B, adjusted EBITDA of $15.244B, FCF of $10.262B, and Q3 AI semiconductor revenue expected at $16.0B.
Marvell May 28, 2026 Q1 FY2027 earnings release: used with the local MRVL lane for Q1 FY2027 revenue of $2.418B, Data Center revenue of $1.833B, GAAP/non-GAAP gross margin of 52.1%/58.9%, Q1 operating cash flow of $638.8M, and Q2 FY2027 revenue guidance of $2.7B +/- 5%.
AMD May 5, 2026 Q1 2026 earnings release and local AMD lane: used for Q1 2026 revenue of $10.253B, Data Center revenue of $5.775B, Q2 revenue guidance near $11.2B, and the remaining proof burden around Instinct revenue, MI450/Helios execution, margins, software, and warrant dilution.
Discovery And Chart Provenance
The chart API reads daily_ohlc from the local discovery store and returns weekly packages using first open, maximum high, minimum low, final close, and summed volume.
Charts show 20w_ema, 100w_ema, weekly_volume, and 20w_average_volume. EMAs are computed from weekly closes using full available weekly history before clipping the visible chart to the latest three years.
Local DuckDB status showed daily OHLC coverage through 2026-06-08: NVDA 1,274 rows and latest close $208.64; AVGO 1,275 rows and latest close $396.60; AMD 1,275 rows and latest close $490.33; MRVL 1,274 rows and latest close $288.85; QCOM 1,274 rows and latest close $217.77.
Technical setup references use completed weekly bars through 2026-06-05 to avoid treating the partial 2026-06-08 week as a full weekly volume signal. The completed-week closes were NVDA $205.10, AVGO $385.73, AMD $466.38, and MRVL $263.47.
Ticker-specific Massive adjusted backfills showed source freshness through 2026-05-08 in prior lineage checks; later grouped daily market updates with ticker=NULL populated stored rows through 2026-06-08. Treat daily_ohlc as the chart source and refresh lineage before using this page for a new market session.
Parent expanded-basket metadata records 5,274 active common stocks and 4,991 active common stocks with at least 64 daily bars and latest parent OHLC coverage through 2026-06-05. This node refresh adds MRVL to the charted core and records stored daily OHLC through 2026-06-08.
Known Gaps
Local 13F holdings were not used for NVDA, AVGO, AMD, or MRVL, so this page does not make holder-concentration claims from local discovery.
QCOM stays watch-only because the local lane says the data-center custom silicon route still lacks customer, product, revenue scale, margin, and contract-duration disclosure. ARM and TSM remain excluded because local discovery lacks instrument and OHLC coverage.
Price and volume context supports setup labels, triggers, and invalidation levels only. It does not establish why a stock moved without same-window earnings, filing, customer, policy, or supply evidence.